`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   11:21:25 12/29/2020
// Design Name:   MULT_DIV
// Module Name:   E:/Codes/Verilog/P6/MIPS/MIPS/TBofDMC.v
// Project Name:  MIPS
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: MULT_DIV
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TBofDMC;

	// Inputs
	reg clk;
	reg reset;
	reg [31:0] D1;
	reg [31:0] D2;
	reg Start;
	reg isHI;
	reg IS_DIV;
	reg IS_Signed;

	// Outputs
	wire [31:0] Data;
	wire busy;

	// Instantiate the Unit Under Test (UUT)
	MULT_DIV uut (
		.clk(clk), 
		.reset(reset), 
		.D1(D1), 
		.D2(D2), 
		.Start(Start), 
		.isHI(isHI), 
		.IS_DIV(IS_DIV), 
		.IS_Signed(IS_Signed), 
		.Data(Data), 
		.busy(busy)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 1;
		D1 = 0;
		D2 = 0;
		Start = 0;
		isHI = 0;
		IS_DIV = 0;
		IS_Signed = 0;

		// Wait 100 ns for global reset to finish
		#95;
        
		// Add stimulus here
		reset = 0;
		Start = 1;
		#10;
		Start = 0;
	end
	always #5 clk = ~clk;
endmodule

